Positions are open for full-time and internship in the areas of CPU and SOC DFT design and verification.
As a SOC/CPU DFT Verification Engineer, you will have the following responsibilities:
- Work closely with architecture, RTL designers, and DFT designers on verifying the functionality correctness of the Design for Test logic
- Reviewing Architecture and Design Specifications
- Develop test plans and test environments
- Develop tests in C/C++ or Python according to the test plans
- Develop coverage monitors and analyze coverage to ensure all test cases in the plans are covered
- Develop checkers or C-based transactors to verify the design
- Work with silicon bringup team on developing tests that work in the emulation and FPGA environments
- Implementing test benches, generating directed/constrained random tests
- Debugging failures, running gate level simulations, tracking bugs and closing coverage
- Handling schedules and supporting multi-functional engineering effort
- Assisting in verification flows, automation scripts and regressions
We are looking for all levels of talent, from entrance to advanced level of experience are all welcome.
- Good knowledge of digital logic design, microprocessor, debug feature, and DFT architecture and CPU architecture, microarchitecture
- Knowledge of DFT and structural debug concepts and methodologies: JTAG, IEEE1500, MBIST, scan dump, memory dump
- Knowledge of Verilog and experience with simulators and waveform debugging tools
- Experience with Verilog / SystemVerilog
- Experience with Perl, Shell scripting, Makefiles, TCL a plus
- Excellent skills in problem solving, written and verbal communication, excellent organization skills, and highly self-motivated.
- Ability to work well in a team and be productive under aggressive schedules.
Education and Experience
PhD, Master’s Degree or Bachelor’s Degree in technical subject area.