ASIC Verification Engineer
At Juniper Silicon group, we push the boundaries of what is possible in a piece of silicon die. We build cutting edge networking chips used to build world-class routers and switches.
Bring your passion and there are no boundaries to what you can accomplish here. We are like a start-up in a big company. Year after year, our group builds the most powerful and highest possible density networking chips.
As part of our fast-paced chip design group, you will become an expert in building high-speed ASICs, from specifications to final netlist. You pick and choose where you want to work on – design, verification or timing closure/PD. We let you explore your passions here.
Open communications, empowerment, innovation, teamwork and customer success are the foundations of the team. Thus, you set your own limits for learning, achievements and rewards.
You will be exposed to latest verification methodologies such as UVM and you will enable complex feature verification suites.
· You will start with a functional specification of a module and come up with a detailed test plan on to verify the module – do not worry, you will have guidance from our senior engineers on how to go about this if you have not done this before.
· You will build the module level test bench using System Verilog/UVM
· You will write tests according to the test plan and find bugs in the module. You will be responsible for making sure your module is fully functional.
· You will learn and use state of the art tools for doing formal verification, code coverage analysis, gate sims, and more.
· You will also get a chance to be part of full chip/sub-system and emulation testing – which gives you exposure to the entire functionality of the chip.
· You get to participate in ASIC validation in the lab if you are passionate about making the chip come alive.
Required and Desired Skills:
· Bachelor’s degree required, Master’s strongly desired in Electrical Engineering or Computer Science/Engineering
· Strong analytical/ problem solving skills.
· Should have taken courses in digital logic design.
· Strong coding skills in Verilog/System Verilog through courses and projects
· Experience in constrained-random verification with methodologies such as UVM is a strong plus.
· Knowledge of Computer Architecture/networking protocols and machine learning through graduate level courses is a plus.
· Knowledge of Perl/Python/C/C++ is a strong plus.
· Excellent written and verbal communications skills is good to have.
We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.