About the team:
You will be part of Intel Advanced Design Organization (AD) within Design Enablement (DE) focused on pathfinding and development of advanced memory technology and circuits to enable best-in-class memory collateral/IP and product design across all generations of Intel process technology.
Our AD organization:
Delivers critical technology & design collaterals to enable future product designs
– Develops the 1st chips for all new Intel technology nodes
– Ensure process and design enablement are robust for high-volume product manufacturing
Critical technologies AD delivers to Intel:
– Digital and Analog Standard Cell Libraries
– Embedded Memory (SRAM, RF, ROM, eDRAM, Fuse, etc.)
– Analog Circuit Reference Designs (PLL, DLL, VR, etc.)
– High-speed I/O Reference Designs (DDR, SerDes, GPIO)
– RF and Wireless Circuits (WaveGuide TX, Power Amplifier)
Advanced Design develops embedded memory technology, array designs, silicon testing on technologies like eDRAM, MRAM and SRAM.
About the role:
As a member of our team, your responsibilities will include (but not limited to):
– Memory pathfinding activities and power performance area (PPA) optimization through design technology co-optimization (DTCO); product/design enablement
– Memory bitcell and complex periphery IC layout and automation
– Memory array/IP design, memory circuit innovation, testchip design/execution/validation
– Pre/post-Si validation/debug to enable yield and parametric tracking/ramp
This is an entry level position and compensation will be given accordingly.
You must possess the below requirements to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates.
The experience listed below would be obtained through a combination of your schoolwork and/or classes and/or research and/or relevant previous job and/or internship experiences.
The requisition you will see with the provided link has the skillset of different positions under the same opening. Therefore, several hiring managers will have the opportunity to review all the candidates, this way you will have the opportunity to showcase your resume to more managers at the same time, a great chance to apply and get matched.
Candidate must possess a minimum of MS with 6+ months industry experience or PhD in Electrical Engineering, Computer Engineering. Must have the required degree by December 2021
Experience in the following:
– ASIC design flow and validation
– Industry-standard CAD tools/flows for digital and/or analog design
– CMOS custom circuit design, simulation, layout design, and verification
– Device physics
– Design, characterization, and verification of custom memory (SRAM, Register File, ROM) circuits
– Design trade-off of power, performance and area
– Design technology co-optimization