Do you have a passion for invention and self-challenge? Do you thrive on pushing the limits of what’s considered feasible? As part of our team, you will be responsible for and contribute to verifying high throughput complex SoCs. Integrating multiple complex IP level DV environment into chip level DV. Crafting highly reusable best-in-class UVM TB, implementing effective coverage driven and directed test cases, deploying new tools and implementing methodologies to improve quality of tape-out readiness. By collaborating with other product development groups across Apple, you’ll push the industry boundaries of what cellular systems can do and improve the product experience for our customers across the world! As a Design Verification Engineer on our team, you’ll be at the center of the verification effort within our silicon design group responsible for designing and productizing state-of-the-art Cellular SoCs! This position requires someone comfortable will all aspects of SoC design verification engineering. Someone that thrives in a dynamic multi-functional organization, is not afraid to debate ideas openly, and is flexible enough to pivot on constantly evolving requirements.
- You bring dedicated/hands-on ASIC DV experience in reusable verification methodology such as UVM, OVM, eRM, VMM, etc.
- With most recent experience in UVM and a consistent track record of working full ASIC cycle from concept to tape-out to bring-up.
- You bring thorough experience in taping out large SoC systems with embedded processor cores and hands-on verification experience of PCIe, LPDDR4 Memory Controller, Bus Fabric, NOC, AHB, AXI, based bus architecture in UVM environment.
- In-depth knowledge and experience working with low power design, UPF integration, power-aware verification, power-aware coverage, boot-up, power-cycling, HW/FW interaction verification will be essential with us.
- You’re a standout collaborator with excellent communication skills, you’re analytic and you dream of tackling diverse challenges.
- Having knowledge of 4G/5G cellular physical layer operation (3GPP) is a plus.
- Beneficial to have Cellular and/or digital communication background.
- Knowledge of assertion-based verification, simulation acceleration greatly valued.
You’ll get a detailed understanding of High Throughput SoC Architecture, standard SoC peripherals such as SPI, I2C, UART, Timers, DMA, memory management schemes, low power spec and power aware testing, multi-processor systems, DDR, PCIe, PLL, debug infrastructure, on-chip security verification, power up schemes. Build coverage driven verification plans from specifications, review and refine to achieve coverage targets. Architect UVM based highly reusable test benches and integrate complex multi-instance VIPs, sub-system test benches and test suites to SoC level, achieve targeted coverage, collaborate with design, architecture, SW, FW, and external IP delivery teams to effectively integrate and verify overall SoC design. Construct detailed test plan to cover key integration use cases, through collaborative work with design, FW, and SW teams. Collaborate with SW, FW, emulation and product testing teams to aid in the verification and debug of boot code, drivers, and test vector generation. Work closely with DV methodology architects to improve verification flow.
BS/MS in EE/CS/CE