KEY JOB FUNCTIONS:
Work with computer architects and RTL designers on sections of a CPU core pipeline and related logic. Participate in defining, coding, and debugging next-generation microarchitecture, and collaborate with other teams on design verification, synthesis, power reduction, timing convergence, and floorplanning.
PREFERRED EDUCATION AND EXPERIENCE:
Knowledge of computer architecture, assembly language coding, high speed logic design, power management, and Verilog coding are desired. Strong problem solving, debugging, communication, and documentation skills, plus a track record of driving tasks to completion, are essential. Familiarity with logic synthesis, design verification, RTL coding methodology, DFT (Design For Test), DFD (Design For Debug), performance simulators, scripting (Ruby, Perl, Shell, Tcl), and physical circuit design concepts/tools (e.g. place & route, area & timing optimization) are a plus.
No experience required. Completion of 2nd year of Computer Engineering, Computer Science, or Electrical Engineering program preferred.