DFT RTL DESIGN COOP:
You will be working with a very experienced team of processor architects and RTL designers developing the Design-For-Test microarchitecture and RTL of a next generation microprocessor. A successful candidate will have relevant course and project work in Processor architectures, DFT, Digital Logic design and RTL coding with Verilog or VHDL. Knowledge in BIST, Scan, JTAG or Testability is a plus.
PREFERRED EDUCATION AND EXPERIENCE:
Senior year MS or PhD candidate in CS/CompE/ECE/EE with in depth knowledge of Processor Design-For-Test Architecture (DFT) or Testability, Digital Logic design & RTL coding; preferably using Verilog for a complex processor unit. Should have good exposure to physical design and verification methods.