Design Verification Engineer
- Understand the architecture of the graphics IP and functional block being designed
- Influence and drive verification environment with a team of engineers
- Participate in the verification of a complex IP block, take ownership of some of the key features
- Debug functional/performance bugs within the graphics IP
- Must have strong knowledge of C / C++ and Verilog / System Verilog.
- Strong analytical thinking and problem solving skills, excellent attention to detail, and good coding skills are required.
- Experience using industry standard tools and adaptability to utilize home grown tools.
- Must be a self-starter, and able to independently drive tasks to completion
- Knowledge of UVM and constrained-random simulation is a plus.
- Must have good English hearing, speaking, reading and writing capabilities.
- Must have good teamwork and interpersonal skills.
- Experience with 3D pipeline and industry graphics standards (DX/OGL/OCL) is a plus
- Experience with digital design verification is a plus
- Master’s or Bachelor’s degree in Electrical or Computer Engineering